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ATmega128
The upper seven bits are the address to which the Two-wire Serial Interface will respond when
addressed by a master. If the LSB is set, the T W I will respond to the general call address ($00),
otherwise it will ignore the general call address.
TWCR
value
TWINT
0
TWEA
1
TWSTA
0
TWSTO
0
TWWC
0
TWEN
1
–
0
TWIE
X
T W EN must be written to one to enable the T W I. The T W EA bit must be written to one to enable
the acknowledgment of the device’s own slave address or the general call address. T W STA and
T W STO must be written to zero.
W hen T W AR and T W CR have been initialized, the T W I waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “0” (write), the T W I will operate in SR mode, otherwise ST mode is entered. After
its own slave address and the write bit have been received, the T W INT flag is set and a valid
status code can be read from T W SR. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in Table 90 . The
slave receiver mode may also be entered if arbitration is lost while the T W I is in the master mode
(see states $68 and $78).
If the T W EA bit is reset during a transfer, the T W I will return a “Not Acknowledge” (“1”) to SDA
after the next received data byte. This can be used to indicate that the slave is not able to
receive any more bytes. W hile T W EA is zero, the T W I does not acknowledge its own slave
address. However, the Two-wire Serial Bus is still monitored and address recognition may
resume at any time by setting T W EA. This implies that the T W EA bit may be used to temporarily
isolate the T W I from the Two-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the T W I is turned off. If the T W EA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep
and the T W I will hold the SCL clock low during the wake up and until the T W INT flag is cleared
(by writing it to one). Further data reception will be carried out as normal, with the AVR clocks
running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may
be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register – T W DR does not reflect the last byte
present on the bus when waking up from these sleep modes.
219
2467X–AVR–06/11
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